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Common terms and phrasesalgorithm Amdahl analysis analytic model approximation Architecture assume assumption average number bandwidth behavior benchmark block size bytes cache memory cache miss cache miss ratio chain computer systems control unit crossbar curves cycle data reference modeling delay delta network dependent derived device disk arrays distribution effects equation error estimate example execution factor footprint function given IEEE IEEE Trans increases instruction-level instruction-level parallelism interleaved latency live lines load LRU replacement main memory Markov Markov chain measured memory module miss rate miss-rate multiple multiprocessor multiprocessor systems multiprogramming node number of processors obtained operations optimal overhead paper parallel parameters percent pipeline prediction prefetch probability problem Proc PU policy queueing model queueing networks random reconnection reduce references reload transient segments simulation results speedup statistics superpipelined superscalar superscalar machine synchronized techniques throughput trace utilization values variables vector workload write References to this bookFrom Google ScholarMappability Estimation Approach for Processor Architecture EvaluationJuha-Pekka Soininen, Jari Kreku, Yang Qu, Martti Forsell Using Constraint Logic Programming in Memory Synthesis for General ...Renate Beckmann, Jürgen Herrmann Fast Processor Core Selection for WLAN Modem using Mappability ...Juha-Pekka Soininen, Jari Kreku, Yang Qu, Martti Forsell Kosten--und Performance--Modellierung von applikationsspezifischen ...Dipl-Ing Hartwig Jeschke References from web pagesIEEE Xplore 2.1 Performance Modeling for Computer Architects Performance modeling for computer architects / 저자/편저자 ... Bibliographic information |