Pentium Processor System ArchitecturePentium Processor System Architecture describes the hardware architecture of computers using Intel's family of Pentium processors, providing a clear, concise explanation of the microprocessor's relationship to the rest of the system. Written for computer hardware and software engineers, this book details Intel's technical strategy behind the Pentium family of processors - not just how Intel designed Pentium, but why. This revised edition expands coverage of virtually every topic and adds new sections on the Pentium 90 and 100MHz (P54C) processors. In addition to pointing out the key differences between 80486 and Pentium system designs, the book explores all the important Pentium features. |
Contents
Documentation Conventions | 5 |
Table 11 Prefetch Queue Depth 10 | 10 |
Eliminates Internal Contention | 13 |
Figure 11 The Pentium Microprocessor Enhancements | 18 |
The Pentium 60 and 66MHz Processors | 21 |
Figure 21 The Pentium Processors Functional Units | 24 |
Functional Unit Description | 28 |
Figure 23 The Elements Comprising the Pentium Processor Bus Unit | 30 |
Figure 79 Burst Read HitL2 Cache | 181 |
viii | 184 |
Table 75 Quadword Address Sequences During Burst Transfers | 185 |
Cycle A Begins | 188 |
Figure 712 Pipelined Read Hit | 190 |
Table 77 Signals Placed on the Bus During a Pipelined Cycle | 191 |
UPipe L2 Miss with Clean Replacement VPipe L2 | 194 |
Figure 713 L2 Cache Miss with Clean Line Replacement | 196 |
Pentium Cache Overview | 35 |
Figure 31 The Cache Memory Concept | 36 |
Figure 33 LookAside Cache Architecture | 43 |
Caching Solution | 50 |
Figure 34 First and Second Level Caches | 51 |
Multiple Processors and the MESI Model | 61 |
Figure 41 State Diagram of MESI Transitions that Occur within the Pentiums Data Cache | 63 |
Second and Subsequent Writes to the Internal Cache | 68 |
Figure 44 Two Processors With Writeback Caches Using the MESI Model | 71 |
Table 42 Initial State of Cache Lines | 72 |
Figure 47 Read Scenario Three | 77 |
Table 43 Initial State of Cache Lines | 80 |
Figure 49 Write Scenario Two | 83 |
Table 44 L1 Cache State Changes During Memory Reads | 89 |
Pentium Signal Interface | 93 |
Figure 51 The Pentium Processor Pinouts | 94 |
Table 51 486 Signals Not Used by the Pentium Processor | 95 |
Table 57 Pentium Processor Addressing Examples | 101 |
The Data | 103 |
Figure 52 The Pentium Processor Data Bus | 104 |
Communication with 81632 and 64bit Devices | 105 |
Figure 55 Data Bus Steering Transceivers Required by 16Bit Devices | 110 |
Bus Cycle Control Signals | 113 |
Table 59 Pentium Processor Bus Cycle Definition | 114 |
Table 511 State of the PCD Pin During Memory Accesses | 124 |
Interrupt Signals | 126 |
DebugTest Signals | 133 |
Figure 61 Overall Block Diagram of the Pentium Processor Paging on | 140 |
Table 61 Examples of Explicit Register Contention | 147 |
Instruction Branch Prediction | 149 |
Figure 65 The Branch Target Buffer | 151 |
Figure 69 Organization of the Code Cache Lines | 154 |
The FloatingPoint Pipeline | 158 |
Table 62 FloatingPoint Pipeline Stages | 159 |
Anatomy of a Read Hit | 164 |
Figure 72 The Structure of the Internal Data Cache | 166 |
Table 71 Data Cache Directory Entries Prior to Sample Reads | 169 |
Anatomy of a Read Miss | 172 |
Figure 76 Internal Data Cache During Read Miss Example | 173 |
Table 73 Bus Cycle Definition for Cache Linefill Request | 177 |
Inquire Cycles | 206 |
30 | 207 |
Table 81 Pentium Processor Bus Cycle Types | 210 |
Figure 81 Timing of a Memory Read Followed by a Memory Write Bus Cycle Non | 213 |
Table 82 Special Cycles | 216 |
Interrupt Acknowledge Bus Cycle | 217 |
System Management Mode SMM | 221 |
Figure 91 Address Space Available to Processor when Operating in Different Modes | 222 |
31 | 229 |
Table 91 Initial Core Register Values for SMM | 231 |
Exiting SMM | 234 |
Figure 101 Control Register 4 CR4 | 237 |
Virtual Paging Extensions | 240 |
Figure 106 The TSS Format | 244 |
New Exceptions | 249 |
Table 102 Internal Hardware Statistics and Index Number | 250 |
Figure 109 EAX Register Contents After Request For Family Model and Stepping Informa | 252 |
Test and Debug | 255 |
Table 111 Bus Transaction Parity Error Action Table | 258 |
Figure 111 Machine Check Address Register | 260 |
Figure 114 Suggested Debug Port Logic | 268 |
Program Debug Features | 270 |
P54C Processor Overview | 281 |
Dual Processor Signals | 287 |
Dual Processors | 295 |
Bus Arbitration in a DualProcessor System | 298 |
Address Snooping in a DualProcessor System | 304 |
The APIC | 317 |
Local Interrupts LINTS Timer Error | 337 |
35 | 352 |
APIC Bus Arbitration | 353 |
38 | 364 |
Local APIC Register Mapping | 370 |
SMI Delivery via APIC Bus | 376 |
The Pentium 61075MHz Processor | 381 |
Glossary of Term | 389 |
Signal Glossary | 405 |
Instruction Pairing Summary | 417 |
References | 423 |
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Common terms and phrases
8-bit device A's L2 cache address bus AHOLD APIC bus APIC ID arbitration branch prediction BRDY bus cycle bus cycle definition bus master byte enable cache coherency cache controller cache directory cache line cache line-fill cacheable chapter clock cycle code cache complete copy data bus Data Path deasserted debug registers detected directory entry dual processor EADS external logic external memory Figure floating-point FLUSH HITM I/O APIC indicates initiates input instruction pipelines internal cache internal data cache interrupt request invalidate L1 data cache latched line fill memory read memory write MESI modified line output P54C processors Pentium processor perform prefetcher priority processor B's L2 processor complex Programmable Interrupt Controller quadword RESET sampled asserted signal SMRAM snoop hit special cycle specified stored subsystem system bus System Management Mode system memory Table target line transceivers transfer U-pipe updated V-pipe vector WB/WT write-back write-through
