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ARQ scheme BCH code binary block code buffer register burst errors burst of length burst-error-correcting byte capable of correcting code of length code polynomial code vector code word computation constraint length convolutional codes coset cyclic code decoding circuit detected EG code encoder error burst error digits error pattern error probability error-correcting capability Example fewer errors Galois field guard space Hamming code Hence hybrid ARQ IEEE Trans information digits information sequence input integer interleaved linear code majority-logic gate metric minimal polynomial minimum distance modulo-2 multiplication n-tuple nonzero number of parity-check obtain orthogonal check sums output parity parity-check digits parity-check matrix path primitive element primitive polynomial received polynomial received sequence received vector receiver buffer retransmission round-trip delay selective-repeat ARQ sequential decoding shown in Figure Step syndrome bits syndrome register systematic code Table Theorem throughput transmitted undetected error Viterbi algorithm Viterbi decoding weight zero
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