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Computer Architecture:

A Quantitative Approach
Front Cover
3 Reviews
Elsevier, Oct 7, 2011 - Computers - 856 pages

The computing world today is in the middle of a revolution: mobile clients and cloud computing have emerged as the dominant paradigms driving programming and hardware innovation today. The Fifth Edition of Computer Architecture focuses on this dramatic shift, exploring the ways in which software and technology in the cloud are accessed by cell phones, tablets, laptops, and other mobile computing devices. Each chapter includes two real-world examples, one mobile and one datacenter, to illustrate this revolutionary change.



  • Part of Intel's 2012 Recommended Reading List for Developers
  • Updated to cover the mobile computing revolution
  • Emphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms.
  • Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends ("What's Next")
  • Includes three review appendices in the printed text. Additional reference appendices are available online.
  • Includes updated Case Studies and completely new exercises.
  

What people are saying - Write a review

User Review - Flag as inappropriate

This is a great book. I purchased without hesitation.
However, the google play version is much more expensive than a paper version, which is hard to believe.
Also, the new edition has some typos
or errors. Unfortunately, some errors in Chapter 5 ( cache coherence) cost me few hours to understand what they really mean.
Besides, I hope online appendix can be put into the google play version.
 

Review: Computer Architecture: A Quantitative Approach

User Review  - Nick Black - Goodreads

The fourth edition is a mighty step up, although this is a classic and well worth having for its expanded historical coverage, pleasantly interwoven in the text as opposed to cold exile on the cdrom. Read full review

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Contents

1 Fundamentals of Quantitative Design and Analysis
1
2 Memory Hierarchy Design
71
3 InstructionLevel Parallelism and Its Exploitation
147
4 DataLevel Parallelism in Vector SIMD and GPU Architectures
261
5 ThreadLevel Parallelism
343
6 WarehouseScale Computers to Exploit RequestLevel and DataLevel Parallelism
431
Appendix A Instruction Set Principles
A-1
Appendix B Review of Memory Hierarchy
B-1
Basic and Intermediate Concepts
C-1
References
R-1
Index
I-1
Translation between GPU terms in book and official NVIDIA and OpenCL terms
I-90
Copyright

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About the author (2011)

Hennessy, Stanford University, Stanford, CA.

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