Advanced Microprocessors

32 bits 4-kbyte addr addressing modes arithmetic byte Chap chip CISC clock Computer condition codes control register Coprocessor Courtesy of Intel Courtesy of Motorola CPU register cycle data bus data cache data register decode destination displacement Doubleword execution fetch flag floating-point instructions IEEE immediate data implemented instruction cache instruction formats instruction pipeline Instruction Set integer Intel Corp interface interrupt Jump kbytes Logical longword Mbytes memory location microprocessors MIPS mod reg r/m Motorola multiply offset opcode operand operation PA-RISC Pentium physical address pipeline POEP POEP-only pointer PowerPC prefetch processor quadword reg1 reg2 register file register indirect RISC RISC-type segment registers selector shift shown in Fig SOEP SPARC specified stack status register string Subtract superscalar SuperSPARC supervisor Table tion trap unit Unsigned vector virtual address word x86 architecture zero