Algorithms for VLSI Physical Design AutomationAlgorithms for VLSI Physical Design Automation is a core reference text for graduate students and CAD professionals. It provides a comprehensive treatment of the principles and algorithms of VLSI physical design. Algorithms for VLSI Physical Design Automation presents the concepts and algorithms in an intuitive manner. Each chapter contains 3-4 algorithms that are discussed in detail. Additional algorithms are presented in a somewhat shorter format. References to advanced algorithms are presented at the end of each chapter. Algorithms for VLSI Physical Design Automation covers all aspects of physical design. The first three chapters provide the background material while the subsequent chapters focus on each phase of the physical design cycle. In addition, newer topics like physical design automation of FPGAs and MCMs have been included. The author provides an extensive bibliography which is useful for finding advanced material on a topic. Algorithms for VLSI Physical Design Automation is an invaluable reference for professionals in layout, design automation and physical design. |
Contents
Foreword | 8 |
Via Minimization and OvertheCell Routing | 8 |
Acknowledgments | 8 |
Copyright | |
18 other sections not shown
Other editions - View all
Common terms and phrases
boundary channel routing problem chip circle graphs circuit clock CMOS compaction complexity components computation connected constraint graph corner stitch cost cutsize data structure defined delay density design automation design rules design style devices doglegs edge electrons example floorplanning FPGA full custom gate array given graph G grid graph high performance horizontal input integer program interconnections intersection interval graph iteration layer layout line segments maximum independent set maze routing method minimize minimum N₁ neighbor netlist node NP-complete number of nets objective function optimal output over-the-cell partitioning algorithms partitioning problem permutation graph phase pin assignment placement algorithms placement problem plist rectangles reduce router routing algorithms routing region shortest path shown in Figure silicon simulated annealing solution standard cell standard cell design Steiner tree step subcircuits switchbox technique terminals total number tracks transistor vertex vertical constraint VLSI wafer weight width wire length