Algorithms for VLSI physical design automation
Algorithms for VLSI Physical Design Automation is a core reference text for graduate students and CAD professionals. It provides a comprehensive treatment of the principles and algorithms of VLSI physical design. Algorithms for VLSI Physical Design Automation presents the concepts and algorithms in an intuitive manner. Each chapter contains 3-4 algorithms that are discussed in detail. Additional algorithms are presented in a somewhat shorter format. References to advanced algorithms are presented at the end of each chapter. Algorithms for VLSI Physical Design Automation covers all aspects of physical design. The first three chapters provide the background material while the subsequent chapters focus on each phase of the physical design cycle. In addition, newer topics like physical design automation of FPGAs and MCMs have been included. The author provides an extensive bibliography which is useful for finding advanced material on a topic. Algorithms for VLSI Physical Design Automation is an invaluable reference for professionals in layout, design automation and physical design.
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Design and Fabrication of VLSI Devices
Data Structures and Basic Algorithms
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antifuses boundary capacitance channel height channel routing problem chip circle graphs circuit clock routing CMOS compaction complexity components computed connected constraint graph cost data structure delay density design cycle design rules design style detailed routing doglegs edge fabrication floorplanning FPGA full custom gate array given global routing graph G grid grid graph high performance horizontal input integer program interconnections intersection interval graph iteration layout logic block maximum independent set maze routing minimize minimum netlist node NP-complete NP-hard number of nets optimal output over-the-cell routing partitioning problem permutation graph phase pin assignment placement algorithms placement problem planar rectangles rectilinear Steiner tree reduce router routing algorithm routing region shown in Figure simulated annealing standard cell standard cell design Steiner tree step subcircuits switchbox technique terminals tile total number transistors vacant vertex vertical constraint VLSI wafer weight wire length wire segments