Applications of VHDL to Circuit Design

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Springer Science & Business Media, Jun 30, 1991 - Computers - 232 pages
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Describing and designing complex electronic systems has become an overwhelming activit)' for which VHDL is showing increasingly useful and promising support. Although created as a description language. VHDL is being increasingly used as a simulatable and synthcsizablcdcsign language. For the first time, here is abook which describesa number of unique and powerful ways VHDL can be used to solve typical design problems in systems •• ones which must be designed correctly in vcry short periodsoflime. Typically useful lcchniquessuch as switch-level modeling, mixed analog and digital modelling, and advanced synthesis for which VHDL showsgrealpromisearefully presented. Thesemethˇ ods are bOlh immedial.ely applicable. and indicale lIle potential of VHDL in efficiently modelling Ihe real worldofelectronic systems. Sinceitsinception.there hasbeen adesireforananalogdescription languageconsistent with (and integrated with) VHDL. Until recently. VHDL could onl)' be applied to digital circuits.ootlhedreamofdescribingandsimulatingmixedanalogand digitalcircuitsis now a reality as described herein. Describing the functionality of analog circuits including intetoperability with digital circuits using the VHDL paradigm is surprisingly easy and powerful. The approach outlined by the authors presages a significant advance in the simulation of mixed systems.
 

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Contents

SwitchLevel Modeling in VHDL
1
111 Overview
2
113 A Switchlevel Modeling Solution in VHDL
3
Interpretative vs Compiled and Global vs Distributed
4
12 Advanced Simulator Programming
6
122 Variables vs Signals c Predefined Attributes
8
123 Concurrent vs Sequential Statements
9
125 Userdefined Types
10
421 Variable Gain Amplifier
101
422 Envelope Detector
103
423 Integrating Capacitor
105
43 Application of PhaseLocked Loop
106
432 Simulation Results
109
441 Single Shot
110
442 PhaseFrequency Detector
111
443 Charge Pump
113

126 ValueSystem and Resolution Functions
11
127 Properties of Resolution Functions
14
13 SwitchLevel Package
15
131 46value System
16
132 Functional Support for the 46value System
18
14 Distributed Algorithm for Passtransistor
22
142 Overview of Algorithm
23
143 Completion of Distributed Algorithm
26
15 VHDL Implementation of Distributed Algorithm
29
16 Examples of Switchlevel Networks
33
162 Memory Cell based on two Inverters
34
163 124 and 6bit adders
35
164 Performance of VHDL Switchlevel simulation
38
17 Future Research
39
174 Analog Models in VHDL
40
Modeling of Transmission Line Effects in Digital Circuits
43
22 Underlying Concepts and Structure
44
222 Identifying and Structuring Modeling Information
45
223 General Model Structure
48
23 Behavior Models
49
231 Lossless Transmission Line
50
232 Receiver
55
233 Linear Driver
57
234 General Driver
60
24 Application of Transmission Line Behaviors
63
242 Network Example
67
243 Simulation Results
69
25 Summary
71
Behavior Modeling of Mixed AnalogDigital Circuits
73
31 Introduction
74
32 Simulation Model
75
322 General Model Structure
78
323 Application to Circuits
79
33 Design Verification Methodology
86
Chip Level
88
34 Application of AnalogDigital Behaviors
89
342 Receiver Model
91
343 Network Example
92
344 Simulation Results
93
345 Limitations
95
35 Summary
96
References
97
Modeling of AnalogDigital Loops in VHDL
99
42 AGC Loop Behavioral Model
100
444 SecondOrder Filter
115
445 Voltage Controlled Oscillator
117
45 Application of PhaseLocked Loop
119
452 Simulation Results
121
453 Limitations and Usage
122
Modeling Style Issues For Synthesis
123
51 What is HDL Synthesis?
124
52 Applying HDL Synthesis Technology
126
522 QualityProductivity Design Automation Acceptance Criteria
128
523 Practical Considerations
130
53 An HDL Synthesis Policy
132
532 Design Style
133
533 Supported Language Constructs
134
54 Synthesis of Register Transfer Level Constructs
136
55 Synthesis Style Issues In VHDL
147
552 Synchronous Operation Through Implicit Storage Elements
149
553 Partially Asynchronous Operation
151
554 Asynchronous Operation
152
56 A Complete Example
153
57 Closing Remarks
160
Modeling of Standard Component Libraries
163
61 Structure of Model Libraries
165
62 Relevant Issues in Logic Simulation
168
63 Layers of Abstraction
169
64 Independence from Physical Packaging
174
65 StrengthLevel Values Set Independence
181
66 Independence from Timing Parameter Values
186
67 Toward a Standard
192
68 Summary
195
Anomalies in VHDL and How to Address Them
197
71 Common Misconceptions about VHDL
198
712 Initialization of Signals
201
713 Working Around the Lack of Global Variables in VHDL
206
714 Use of out and buffer Mode Ports
211
715 Use of Bus and Register Signals
214
716 Predefined Signal Attributes
217
72 VHDL Language Inconsistencies
221
722 Spaces in Abstract Physical Literals
223
723 Null Slices
225
725 Resolution Function Parameters
226
73 Summary
228
Index
229
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