CMOS Digital Integrated Circuits: Analysis and Design
This text is the most complete book on the market for CMOS circuits. Aimed at junior/senior courses offered in electrical engineering and computer science, this book starts with CMOS processing, and then covers MOS transistor models, basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, BiCMOS circuits, I/O circuits, VLSI design methodologies, low-power design techniques, design for manufacturability and design for testablility. This text provides rigourous treatment of basic design concepts with detailed examples. It typicaly addresses both the computer-aided analysis issues and the design issues form most of the circuit examples. Numerous SPICE simulation results are also provided for illustration of basic concepts. Through rigorous analysis of CMOS circuits in this text, students will be able to learn the fundamentals of CMOS VLSI design, which is the drivng force behind the development of advanced computer hardware.
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FABRICATION OF MOSFETs
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CMOS digital integrated circuits: analysis and design
Sung-Mo Kang,Yusuf Leblebici
Snippet view - 2003
adder assume BiCMOS bit line calculate capacitor cell channel length CHAPTER charge chip circuit design Cload clock signal CMOS inverter column current equation current-voltage density depletion region depletion-load design rules device diffusion regions digital circuits doping drain current driver transistor dynamic Dynamic Logic enhancement-type equal fabrication Figure full adder function implementation input voltage integrated circuits interconnect line inverter circuit junction capacitance latch circuit layer linear region logic gate logic-high mask layout minimum MOS Logic Circuits MOSFET n-channel nMOS transistor node voltage noise margins Note output load capacitance output node output voltage p-type parameters parasitic capacitances pass transistor pMOS polysilicon power consumption power dissipation power supply voltage precharge propagation delay pull-down ratio resistive-load resistor shown in Fig simple simulation SPICE static structure substrate bias surface switching threshold voltage transmission gate typical VLSI voltage level Voul width