Technical Publications, Jan 1, 2009 - 520 pages
Basic structure of computersComputer types, Functional unit, Basic OPERATIONAL concepts, Bus structures, Software, Performance, Multiprocessors and multi computers. Data representation. Fixed point representation. Floating - Point representation. Error detection codes. Register transfer language and microoperationsRegister transfer language, Register transfer bus and memory transfers, Arithmetic micro operations, Logic micro operations, Shift micro operations, Arithmetic logic shift unit. Instruction codes. Computer registers computer instructions, Instruction cycle, Memory : Reference instructions. Input/output and interrupt. STACK organization, Instruction formats. Addressing modes. Data transfer and manipulation. Program control. Reduced instruction set computer.Microprogrammed controlControl memory, Address sequencing, Microprogram example, Design of control unit hard wired control, Microprogrammed control.Computer arithmeticAddition and subtraction, Multiplication algorithms, Division algorithms floating-point arithmetic operations. Decimal arithmetic unit decimal arithmetic operations.The memory systemBasic concepts semiconductor RAM memories. Read-only memories, Cache memories performance considerations, Virtual memories secondary storage. Introduction to RAID.Input/output organizationPeripheral devices, Input/output interface, Asynchronous data transfer modes of transfer, Priority interrupt direct memory access, Input/output processor (IOP) serial communication; Introduction to peripheral component, Interconnect (PCI) bus, Introduction to standard serial communication protocols like RS232, USB, IEEE1394.Pipeline and vector processing Parallel processing, Pipelining, Arithmetic pipeline, Instruction pipeline, RISC pipeline vector processing, Array processors.MultiprocessorsCharacteristics of multiprocessors, Interconnection structures, Interprocessor arbitration, Inter processor communication and synchronization cache coherence, Shared memory multiprocessors.
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2's complement addressing modes algorithm Arithmetic shift asynchronous binary block buffer bytes cache coherence cache memory circuit clock cycles common bus Computer Organisation configuration connected contents of register control signals control unit CPU registers data bus data transfer decoder diagram error example execution exponent fetch floating point floating-point format Full Adder function hardware I/O device implementation input instruction pipelining interrupt interrupt request loaded logic magnetic main memory mantissa memory access memory address memory location Memory module microinstruction Microoperations Microprogrammed Microprogrammed Control multiple multiplicand multiprocessor multiprocessor system number of bits opcode operand output parallel parity bit PCI bus performance peripheral printers processing processor processor registers protocol request result RISC sequence serial shared memory shift right shown in Fig shows specified speed stack storage stored subtraction system bus Table tape technique tri-state buffers vector word write