Digital ElectronicsNumber Systems :Binary, Octal, Decimal, Hexadecimal-Number base conversions-complements-signed binary numbers. Binary arithmetic-Binary codes : Weighted - BCD-2421- Gray code - Excess 3 code - ASCII - Error detecting code - Conversion from one code to another - Boolean postulates and laws - De-Morgan's theorem, Principle of Duality - Boolean expression - Boolean function - Minimization of Boolean expressions - Sum of Products (SOP) - Product of Sums(POS) - Minterm - Maxterm - Canonical forms - Conversion between canonical form - Karnaugh map minimization - Don't care conditions.Logic Gates :AND, OR , NOT, NAND, NOR, Exclusive - OR and Exclusive - NOR - Implementations of logic functions using gates, NAND-NOR implementations - Multi level gate implementations - Multi output gate implementations. TTL and CMOS logic and their characteristics - Tristate gates. Combinational Circuits :Design procedure - Adder - Subtractors - Serial adder/Subtractor - Parallel adder/Subtractor - Carry look ahead adder - BCD adder - Magnitude comparator - Multiplexer/Demultiplexer - Encoder/Decoder - Parity checker - Code converters. Implementation of combinational logic using MUX, ROM, PAL and PLA.Sequential Circuit :Flip flops SR, JK, T, D and Master slave - Characteristic table and equation - Application table - Edge triggering - Level triggering - Realization of one flip flop using other flip flops - Asynchronous / Ripple counters - Synchronous counters - Modulo - n counter - Classification of sequential circuits - Moore and Mealy - Design of synchronous counters; State diagram - State table - State minimization - State assignment - ASM - Excitation table and maps - Circuit implementation register - Shift registers - Universal shift register - Shift counters - Ring counters.Asynchronous Sequential Circuits :Design of fundamental mode and pulse mode circuits - Primitive state / flow table - Minimization of primitive state table - State assignment - Excitation table - Excitation map - cycles - Races - Hazards : Static - Dynamic - Essential - Hazards elimination.Memory DevicesClassification of memories - RAM organization - Write operation - Read operation - Memory cycle - Timing wave forms - Memory decoding - Memory expansion - Static RAM Cell - Bipolar RAM cell MOSFET RAM cell - Dynamic RAM cell - ROM organization - PROM - EPROM - EEPROM - EAPROM - Programmable logic devices - Programmable logic Array (PLA) - Programmable Array Logic (PAL). Field Programmable Gate Arrays (FPGA). |
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Contents
Table of Contents | 1-1 |
Chapter 2 Boolean Algebra and Switching Functions 2 1 to 2 | 2-1 |
Appendix A Algorithmic State Machines ASM A1 to A68 | 2-68 |
Chapter 3 Logic Gates 31 to 3 98 | 3-98 |
Chapter 4 Combinational Circuits 41 to 4142 | 4-1 |
Chapter 6 Counters 61 to 6 28 | 5-6 |
Chapter 7 Analysis and Design of Clocked Sequential Circuits 7 1 to 7 | 7-3 |
Chapter 7 Analysis and Design of Clocked Sequential Circuits 71 to 7 74 | 7-74 |
Chapter 9 Asynchronous Sequential Circuits 9 1 to 9 | 9-1 |
Chapter 10 Hazards u 101 to 10 | 9-10 |
Review Questions 5 35 | 10-5 |
Graphical Procedure 324 | 3 |
Appendix A Algorithmic State Machines ASM A 1 to A 68 | A-4 |
Chapter8 Registers 8 110838 | A-8 |
Appendix B Typical Digital ICs 9H9BHHHIHHI B 1 to B | C-4 |
Chapter 8 Registers 81 to 8 38 | 8-8 |
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Common terms and phrases
2-input 9's complement A B C ABCD active low adjacent asynchronous BC BC BCD code BCD number binary code binary number Bit location Boolean expression Boolean function carry CD CD CD cell clock pulse CMOS combinational circuit complement method connected counter decimal number decoder devices Digital Electronics diode enable input encoder equivalent error Example Excess-3 Excess-3 code excitation table fan-out flip-flop full-adder gray code Hamming code hexadecimal hexadecimal number implementation input variables Inputs Outputs inverter JK flip-flop K-map simplification Karnaugh map latch logic circuit Logic diagram logic gates logic symbol maxterms minterms multiplexer NAND gate number of inputs number system octal open collector operation parity bit pin diagram product terms propagation delay quad radix represent sequence sequential circuit serial shift register shown in Fig shows simplified Solution SOP form Step subtraction sum of products sum terms switching transistor truth table
Bibliographic information
| Title | Digital Electronics |
| Author | D.A.Godse A.P.Godse |
| Publisher | Technical Publications, 2008 |
| ISBN | 8184314116, 9788184314113 |
| Length | 837 pages |
| Export Citation | BiBTeX EndNote RefMan |