Interconnect-Centric Design for Advanced SOC and NOC
Jari Nurmi, H. Tenhunen, J. Isoaho, Axel Jantsch
Springer Science & Business Media, Mar 20, 2006 - Technology & Engineering - 454 pages
In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design.
Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design.
The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.
What people are saying - Write a review
We haven't found any reviews in the usual places.
Global Interconnect Analysis
Heiko Zimmer and Axel Jantsch
Bus Structures in NetworksonChip
Jan Madsen Shankar Mahadevan and Kashif Virk
Other editions - View all
abstraction application arbitration architecture bandwidth buffers buses capacitance chip circuit clock distribution clock distribution network clock signal coding communication components Computer Computer-Aided Design configuration connected constraints crossbar switches crosstalk cycle decoder decoupled decreases Design Automation Conference design methodology driver encoding energy error example fat tree frequency functional cores global IEEE implementation increases Integrated Circuits integration interconnect core interface IP blocks IPv6 latency layer line inductance line width logic master MicroNetwork minimum module multiple Networks on Chip nodes on-chip operation optimized optimum output port packets parameters performance pipelined platform power consumption power dissipation processor propagation delay protocol reduce request requirements resource RLC line routing algorithms scheduling scheme self-timed signal propagation delay SiliconBackplane simulation slave socket switching synchronous system-on-chip tasks techniques throughput topology traffic transfer transition transmission variable Viper VLSI voltage wires