Logic Synthesis Using SynopsysŪ

Front Cover
Springer Science & Business Media, 1997 - Computers - 322 pages
0 Reviews
Logic Synthesis Using SynopsysŪ, Second Edition is for anyone who hates reading manuals but would still like to learn logic synthesis as practised in the real world. Synopsys Design Compiler, the leading synthesis tool in the EDA marketplace, is the primary focus of the book. The contents of this book are specially organized to assist designers accustomed to schematic capture-based design to develop the required expertise to effectively use the Synopsys Design Compiler. Over 100 `Classic Scenarios' faced by designers when using the Design Compiler have been captured, discussed and solutions provided. These scenarios are based on both personal experiences and actual user queries. A general understanding of the problem-solving techniques provided should help the reader debug similar and more complicated problems. In addition, several examples and dc_shell scripts (Design Compiler scripts) have also been provided.
Logic Synthesis Using SynopsysŪ, Second Edition is an updated and revised version of the very successful first edition.
The second edition covers several new and emerging areas, in addition to improvements in the presentation and contents in all chapters from the first edition. With the rapid shrinking of process geometries it is becoming increasingly important that `physical' phenomenon like clusters and wire loads be considered during the synthesis phase. The increasing demand for FPGAs has warranted a greater focus on FPGA synthesis tools and methodology. Finally, behavioral synthesis, the move to designing at a higher level of abstraction than RTL, is fast becoming a reality. These factors have resulted in the inclusion of separate chapters in the second edition to cover Links to Layout, FPGA Synthesis and Behavioral Synthesis, respectively. Logic Synthesis Using SynopsysŪ, Second Edition has been written with the CAD engineer in mind. A clear understanding of the synthesis tool concepts, its capabilities and the related CAD issues will help the CAD engineer formulate an effective synthesis-based ASIC design methodology. The intent is also to assist design teams to better incorporate and effectively integrate synthesis with their existing in-house design methodology and CAD tools.
 

What people are saying - Write a review

We haven't found any reviews in the usual places.

Contents

HighLevel Design Methodology Overview
1
12 Design Compiler Basics
19
13 Classic Scenarios
28
VHDLVerilog Coding for Synthesis
33
The Language Issue
40
23 Finite State Machines
44
24 HDL Coding Examples
57
25 Classic Scenarios
65
FPGA Synthesis
197
72 Xilinx 4000 Architecture
198
73 Synopsys Setup synopsys_dcsetup For Xilinx
202
74 Synopsys FPGA Compiler Flow
203
Design for Testability
209
82 Test Synthesis Using Test Compiler
213
83 DesignSpecific Issues in Test Synthesis
217
84 Clock Skew
223

Pre and PostSynthesis Simulation
75
32 File Text IO in VHDL Using the TEXTIO Package
82
33 VHDL Gate Level Simulation
87
35 Classic Scenarios
88
Constraining and Optimizing Designs I
97
42 Clock Specification for Synthesis
102
43 Design Compiler Timing Reports
103
44 Commonly Used Design Compiler Commands
109
45 Strategies for Compiling Designs
115
47 Guidelines for Logic Synthesis
120
48 Classic Scenarios
122
Constraining and Optimizing Designs II
139
52 Fixing Min Delay Violations
146
54 Translating Designs with BlackBox Cells
147
55 Pad Synthesis
149
56 Classic Scenarios
150
Links to Layout
175
62 Floorplanning
176
63 Link to Layout Flow Using FloorPlan Manager
177
64 Basic Links to Layout Commands
184
66 ReOptimizing Designs After PR
186
67 Classic Scenarios
189
85 Test Compiler Default Test Protocol
230
86 Test Compiler Tips
231
87 Examples Showing the Entire Test Synthesis Flow
232
88 Classic Scenarios
233
CAD Tools
245
92 Forward and Backannotation
250
93 Design Compiler InputOutput Formats
255
Design Reuse Using DesignWare
263
102 Inferring Complex Cells
264
103 Creating Your Own Design Ware Library
269
104 Classic Scenarios
276
Behavioral Synthesis An Introduction
283
112 Behavioral Synthesis Concepts
285
113 Synopsys Behavioral Compiler
287
114 Behavioral Synthesis Design Flow
288
115 Example Using Behavioral Compiler
289
116 Behavioral Compiler Reports
295
117 Is Behavioral Synthesis Right For You?
297
APPENDIX A
301
Sample Synopsys Technology Library
311
Sample Synopsys Technology RAM Library Model
314
Copyright

Other editions - View all

Common terms and phrases

References to this book

All Book Search results »

Bibliographic information