On-Chip Communication Architectures: System on Chip Interconnect
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.
On-Chip Communication Architecures is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.
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CHAPTER 3 OnChip Communication Architecture Standards
CHAPTER 4 Models for Performance Exploration
CHAPTER 5 Models for Power and Thermal Estimation
CHAPTER 6 Synthesis of OnChip Communication Architectures
CHAPTER 7 Encoding Techniques for OnChip Communication Architectures
CHAPTER 8 Custom BusBased OnChip Communication Architecture Design
CHAPTER 9 OnChip Communication Architecture Refinement and Interface Synthesis
CHAPTER 10 Verification and Security Issues in OnChip Communication Architecture Design
CHAPTER 11 Physical Design Trends for Interconnects
CHAPTER 12 NetworksOnChip
CHAPTER 13 Emerging OnChip Interconnect Technologies