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An Overview of VLSI Algorithms and Architectures
Concurrent VLSI Architectures
On the Design of Algorithms for VLSI Systolic Arrays
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applications arithmetic array processor band matrix bandwidth bit-serial bitonic sort block bubble sort cache cessors circuit communication complexity Computer Science concurrent Conf connected Cordic data dependence data flow efficient engineering evaluation example execution Figure floating-point frame buffer functions global graph H. T. Kung hardware heapsort host IEEE Trans image processing implementation initial vector input integer interconnection ISBN iterations layout Leiserson linear array logic loop mapping matrix matrix multiplication memory mesh method MIMD module multiplication nodes operations optimal output partitioned PE's performance pipelined pixel polynomial priority queue problem Proc processing elements processor array recurrence requires result RISC Section sequential shear-sort shift register shown in Fig signal processing SIMD sorting algorithm special-purpose speed stack step storage structure systolic algorithm systolic array techniques tion transform tree triangular unit values variable vector VLSI chip VLSI Systems Warp array wavefront array wires