This book covers the spectrum of the testing problem. Areas covered include fault modeling, test generation, fault simulation, memory testing, design for testability, testability measures, PLA testing, and test equipment. The use of this volume will provide a good insight into the VLSI challenges in the area of testing - an area that has become increasingly important due to the emphasis on quality of VLSI products, and the associated costs. As a result, there has been a rapid expansion in the technologies associated with testing, and it is this technological growth which is reflected in the contributions to this volume.
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Introduction to the Series
Test Generation and Fault Simulation
Easily Testable PLA Design
4 other sections not shown
algorithms applied assigned backtrace BILBO bit lines cell chip circuit CMOS combinational logic combinational logic network complement complex components Computers decoder delay Design for Testability detected device DHSFT dynamic electronics error correction example failure fanout fault coverage fault machine fault model fault simulation Feedback Shift Register functional test hardware IEEE implementation International Test Conference latch LFSR Linear Feedback Shift logic gate logic values LSSD networks microprocessor module multiple faults nMOS node operation output lines overhead parity primary inputs primary output printed wiring boards probe problem product lines Programmable Logic Arrays pseudo-random random redundant retry robot Scan Path Self-Testing sensitivity sequence sequential short shown in Figure signal single cp faults speed storage structure stuck-at faults stuck-open fault system clock techniques test engineer test patterns test set tester transistor transistor-level Tuszynski untestable vector vendors VLSI voltage