VHDL Modeling and Design Flow
VLSI : Complete VLSI design flow (with reference to an EDA tool), Sequential, Data flow and structural modeling, Functions, Procedures, Attributes, Test benches, Synthesizable and non-synthesizable statements; Packages and configurations modeling in VHDL with examples of circuits such as counters, Shift registers, Bidirectional bus, etc.
FSM and Sequential Logic Principles
Sequential circuits, Meta-stability synchronization, Design of finite state machines and state minimization, FSM CASE STUDIES - Traffic light control, Lift control and UART, STA and DTA.
Programmable Logic Devices
The CPLDs, Study of architecture of CPLD and study of the architecture of FPGA.System On Chip
One, Two phase clock, Clock distribution, Power distribution, Power optimization, SRC and DRC, Design validation, Global routing, Switch box routing, Off chip connections, I/O architectures, Wire parasitics,
EMI immune design, Study of memory-Basics of memory includes types of memory cells and memory architectures, Types of memory based on architecture specific and application specific viz. SRAM, DRAM, SDRAM, FLASH, FIFO.
CMOS parasitics, Equivalent circuit, Body effect, Technology scaling, parameter, Detail study of inverter characteristics, Power dissipation, Power delay product, CMOS combinational logic design and W/L calculations, Transmission gates, Introduction to CMOS layout.
Need of design for testability, Introduction to fault coverage, Testability, Design-for-Testability, Controllability and Observability, Stuck-at Fault Model, Stuck-Open and Stuck-Short faults, Boundary scan check, JTAG technology, TAP controller and TAP controller state diagram, Scan path, Full and Partial scan, BIST.
Review Questions 219
Chapter 4 Simulation and Synthesis 4 1 to 4
Chapter 5 Sequential Logic Principles 51 to 58
Chapter6 FSM 61 to 656
Introduction to the CPLDs Study of architecture of CPLD and study of the architecture of FPGA
UnitIV System On Chip Chapter
Review Questions 7114
As per Revised Syllabus of University of Pune UoP 2003 Course
Chapter 9 CMOS VLSI 9 1 to 9
UnitV CMOS VLSI Chapter
Other editions - View all
antifuse architecture ASIC begin behaviour block diagram boolean capacitance cells chip clock CMOS combinational logic component instantiation concurrent statements configuration connected constraints CPLD declaration decoder defined delay design entry downto end process entity EPROM example executed finite state machine flip-flop following Fig FPGA gate array gate level hardware IEEE.std_logic_1164.all implement integer interconnect JTAG language level simulation library IEEE logic blocks logic circuits loop statement macrocell Mealy machine memory element Moore machine netlist operand operators optimization package parameters pins place and route PLDs procedure process statement product terms Programmable Logic Devices programming registers reset sequence sequential circuit sequential statements shown in Fig shown in following signal assignment specification SRAM standard std_logic structure subprogram switches synchronous synthesis tools test bench transistors variable Verilog VHDL VHDL code VLSI voltage WAIT statement wires Xilinx