8085 MICROPROCESSOR: PROGRAMMING AND INTERFACINGThis up-to-date and contemporary book is designed as a first level undergraduate text on micro-processors for the students of engineering (computer science, electrical, electronics, telecommunication, instrumentation), computer applications and information technology. It gives a clear exposition of the architecture, programming and interfacing and applications of 8085 microprocessor. Besides, it provides a brief introduction to 8086 and 8088 Intel microprocessors. The book focusses on : microprocessors starting from 4004 to 80586. instruction set of 8085 microprocessor giving the clear picture of the operations at the machine level. the various steps of the assembly language program development cycle. the hardware architecture of microcomputer built with the 8085 microprocessor. the role of the hardware interfaces: memory, input/output and interrupt, in relation to overall microcomputer system operation. peripheral chips such as 8255, 8253, 8259, 8257 and 8279 to interface with 8085 microprocessor and to program it for different applications. |
Contents
8085 MICROPROCESSOR 2549 | 25 |
INSTRUCTION SET INTEL 8085 50121 | 50 |
FUNDAMENTALS OF PROGRAMMING 122152 | 122 |
SEMICONDUCTOR MEMORY 153167 | 153 |
INPUTOUTPUT INTERFACE 168186 | 168 |
PROGRAMMABLE PERIPHERAL INTERFACE 8255A 187205 | 187 |
PROGRAMMABLE INTERNAL TIMER 8253 206221 | 206 |
PROGRAMMABLE INTERRUPT CONTROLLER 8259A 222241 | 222 |
PROGRAMMABLE DMA CONTROLLER 8257 242255 | 242 |
SERIAL DATA TRANSFER 256271 | 256 |
PROGRAMMABLE KEYBOARDDISPLAY | 272 |
Software Operation | 278 |
8086 MICROPROCESSOR ARCHITECTURE 287298 | 287 |
8086 PINCONFIGURATION 299318 | 299 |
Instruction Set Operation Codes in Hexadecimal | 319 |
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Common terms and phrases
8-bit data 8085 microprocessor address bus address is available address lines addressing mode ALP statement Arithmetic Logic Unit BDB T4 BDBM buffer carry flag chip circuit clock control signals control word count data bus data transfer decoding digit display RAM enable EOI command EPROMS execution flags are affected HLDA I/O device incremented indirect addressing mode Initialize input instruction cycle INTA interface interrupt acknowledge interrupt request INTR IO/M keyboard latch loaded machine cycle Macro RTL mask memory location Micro mnemonic opcode Operand operation code OPFMC output PC PC Pin Configuration port Port-A priority processor program counter Read Only Memory Read/Write register pair RESET rotate S₁ scan segment register selected serial data seven segment display shown in Fig single byte instruction stack pointer status strobed subroutine SYNC character synchronous T₁ Write zero