The Verilog® Hardware Description LanguageThis text presents the IEEE 1364-2001 standard of the Verilog language. The examples in this edition have been updated to illustrate the features of the language. A cross referenced guide to these features is provided, thus, designers already familiar with Verilog can quickly learn the features. Newcomers to the language can use it as a guide for reading "old" specifications.; The book should prove to be a useful resource for engineers and students interested in describing, simulating and synthesizing digital systems. It is also ready for use in university courses, having been used for introductory logic design and simulation through advanced VLSI design courses. An appendix with tutorial help and a work-along style is keyed into the introduction for new students. Material supporting a computer-aided design course on the inner working of simulators is also included.; "The Verilog TM Hardware Description Language" includes a CD containing Simucad's Silos TM 2001 Verilog Simulator, examples from the book and lecture slides. The simulator is limited in the size of descriptions it will simulate. A few of the language constructs are not recognized by this version of the simulator. |
Contents
Getting Started | 2 |
Behavioral Modeling of Combinational Circuits | 11 |
Module Hierarchy | 21 |
Summary | 27 |
2 | 35 |
Details of the Functional Datapath Modules | 60 |
Summary on Logic Synthesis | 66 |
Behavioral Modeling 73 | 72 |
MealyMoore Machine Specifications | 203 |
Introduction to Behavioral Synthesis | 209 |
Advanced Timing | 211 |
40 | 235 |
UserDefined Primitives | 239 |
Projects | 283 |
220 | 288 |
Tutorial Questions and Discussion | 293 |
Loops | 82 |
Functions and Tasks | 91 |
Rules of Scope and Hierarchical Names | 102 |
Concurrent Processes | 109 |
A Concurrent Process Example | 122 |
Procedural Continuous Assignment | 136 |
Arrays of Instances | 150 |
Logic Level Modeling 157 | 156 |
Delay Paths Across a Module | 187 |
CycleAccurate Specification | 195 |
Other editions - View all
The Verilog® Hardware Description Language Donald E. Thomas,Philip R. Moorby No preview available - 2014 |
Common terms and phrases
adder assign statement attribute_instance begin end behavioral model bus master bytes casez circuit clock edge clock signal combinational logic constant_expression continuous assignment cycle cycle-accurate dataLines datapath declared DEdgeFF default defined delay delay3 described drive strength element encoded end endmodule endcase endmodule Example endtask eSeg event control event list executed expression fanout fillBits finite state machine flip flop full adder function gate instances gate level gate primitives getMask hexadecimal hierarchical name iClear identifier IEEE IEEE Std implementation initial statement inout input integer latch loaded logic synthesis logic values loop ment module NAND gate negedge nextState non-blocking assignment operands operator output reg parameter ports posedge clock positive edge procedural assignment reset scheduled sequential shown in Example signal signed simulation specified Strong1 syntax synthesis tool task trireg update event vector Verilog Verilog description wait wire write XOR gates zero