Retargetable Code Generation for Digital Signal ProcessorsAccording to market analysts, the market for consumer electronics will con tinue to grow at a rate higher than that of electronic systems in general. The consumer market can be characterized by rapidly growing complexities of appli cations and a rather short market window. As a result, more and more complex designs have to be completed in shrinking time frames. A key concept for coping with such stringent requirements is re-use. Since the re-use of completely fixed large hardware blocks is limited to subproblems of system-level applications (for example MPEG-2), flexible, programmable pro cessors are being used as building blocks for more and more designs. Processors provide a unique combination offeatures: they provide flexibility and re-use. The processors used in consumer electronics are, however, in many cases dif ferent from those that are used for screen and keyboard-based equipment, such as PCs. For the consumer market in particular, efficiency of the product plays a dominating role. Hence, processor architectures for these applications are usually highly-optimized and tailored towards a certain application domain. |
Contents
INTRODUCTION | 1 |
12 HWSW CODESIGN OF EMBEDDED SYSTEMS | 2 |
13 EMBEDDED SOFTWARE DEVELOPMENT | 5 |
14 DSP ALGORITHMS AND ARCHITECTURES | 8 |
15 PROBLEMS AND SOLUTION APPROACH | 14 |
16 OVERVIEW OF RELATED WORK | 18 |
17 GOALS AND OUTLINE OF THE BOOK | 27 |
PROCESSOR MODELLING | 29 |
CODE GENERATION | 85 |
42 PROGRAM REPRESENTATIONS | 86 |
43 RELATED WORK | 89 |
44 THE CODE GENERATION PROCEDURE | 91 |
45 DFL LANGUAGE ELEMENTS | 95 |
46 INTERMEDIATE REPRESENTATION | 98 |
47 CODE SELECTION BY TREE PARSING | 105 |
48 RT SCHEDULING | 118 |
22 THE MSSQ COMPILER | 33 |
23 APPLICATION STUDIES | 36 |
INSTRUCTIONSET EXTRACTION | 45 |
32 ANALYSIS OF CONTROL SIGNALS | 48 |
33 BINARY DECISION DIAGRAMS | 51 |
34 INSTRUCTIONSET MODEL | 52 |
35 INTERNAL PROCESSOR MODEL | 59 |
36 BEHAVIORAL ANALYSIS | 60 |
37 STRUCTURAL ANALYSIS | 68 |
38 POSTPROCESSING | 78 |
39 EXPERIMENTAL RESULTS | 80 |
310 ISE AS A VALIDATION PROCEDURE | 82 |
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Common terms and phrases
access graph ACCU address assignment address register AGU operations algorithm AR[ARP architectures array references ASIP background register basic block binary binary decision diagrams Boolean function code compaction code quality code selection computed constraints control signals control steps cost data moves data-path delay lines denotes DFTs DSP algorithms edges embedded embedded systems encoded expression tree GRTPs guarded assignments hardware heuristic input instruction format instruction set instruction word instruction-level parallelism instruction-set extraction iteration language LOAD loop machine code memory MIMOLA mode register module variable MSSQ multiply-accumulate nodes optimal outp output partial instructions problem processor model REG.R REG1 register allocation register file register transfer representation retargetable compilers ring buffer RT expression RT patterns RT scheduling rules source code specification standard DSPs structure subtree target processor tree grammar tree parser tree parsing vertical code
Popular passages
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Page 204 - Man. A graph based processor model for retargetable code generation . European Design & Test Conference, 1996.
Page 201 - A. Jerraya: Address Calculation for Retargetable Compilation and Exploration of Instruction- Set Architectures, 33rd Design Automation Conference (DAC), 1996 [123] P.
Page 200 - C. Liem, T. May, P. Paulin: Instruction- Set Matching and Selection for DSP and ASIP Code Generation, European Design and Test Conference (ED fc TC), 1994, pp.
Page 203 - P. Paulin, C. Liem, T. May, S. Sutarwala, "DSP Design Tool Requirements for Embedded Systems: A Telecommunications Industrial Perspective", to appear in Journal of VLSI Signal Processing (special isssue on synthesis for real-time DSP), Kluwer Academic Publishers, 1994.
Page 203 - May, and S. Sutarwala. FlexWare: A Flexible Firmware Development Environment for Embedded Systems.