The Verilog® Hardware Description Language

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Springer Science & Business Media, Sep 11, 2008 - Technology & Engineering - 386 pages
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XV From the Old to the New xvii Acknowledgments xx| Verilog A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits 11 Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Procedural Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("
 

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Contents

Verilog A Tutorial Introduction
1
11 Getting Started
2
112 Simulating the binaryToESeg Driver
4
113 Creating Ports For the Module
7
114 Creating a Testbench For a Module
8
12 Behavioral Modeling of Combinational Circuits
11
121 Procedural Models
12
122 Rules for Synthesizing Combinational Circuits
13
67 Summary of Assignment Statements
189
68 Summary
190
69 Exercises
191
CycleAccurate Specification
195
712 A Few Notes
197
72 CycleAccurate Specification
198
722 InputOutput Relationships of an Always Block
199
723 Specifying the Reset Function
202

13 Procedural Modeling of Clocked Sequential Circuits
14
131 Modeling Finite State Machines
15
132 Rules for Synthesizing Sequential Systems
18
133 NonBlocking Assignment
19
14 Module Hierarchy
21
143 Tying the Whole Circuit Together
22
144 Tying Behavioral and Structural Models Together
25
15 Summary
27
16 Exercises
28
Logic Synthesis
35
212 Disclaimer
36
22 Combinational Logic Using Gates and Continuous Assign
37
23 Procedural Statements to Specify Combinational Logic
40
232 Complications Inferred Latches
42
233 Using Case Statements
43
234 Specifying Dont Care Situations
44
235 Procedural Loop Constructs
46
24 Inferring Sequential Elements
48
242 Flip Flop Inferences
50
243 Summary
52
26 Describing Finite State Machines
53
262 An Alternate Approach to FSM Specification
56
27 Finite State Machine and Datapath
58
273 Details of the Functional Datapath Modules
60
274 Wiring the Datapath Together
61
275 Specifying the FSM
63
28 Summary on Logic Synthesis
66
29 Exercises
68
Behavioral Modeling
72
32 If Then Else
75
321 Where Does The ELSE Belong?
80
322 The Conditional Operator
81
33 Loops
82
332 Exiting Loops on Exceptional Conditions
85
34 Multiway Branching
86
343 Comparison of Case and IfElself
89
344 Casez and Casex
90
35 Functions and Tasks
91
351 Tasks
93
352 Functions
97
353 A Structural View
100
36 Rules of Scope and Hierarchical Names
102
362 Hierarchical Names
105
37 Summary
106
Concurrent Processes
109
42 Events
111
421 Event Control Statement
112
422 Named Events
113
43 The Wait Statement
116
431 A Complete ProducerConsumer Handshake
117
432 Comparison of the Wait and While Statements
120
433 Comparison of Wait and Event Control Statements
121
44 A Concurrent Process Example
122
45 A Simple Pipelined Processor
128
452 Synchronization Between Pipestages
130
46 Disabling Named Blocks
132
47 IntraAssignment Control and Timing Events
134
48 Procedural Continuous Assignment
136
49 Sequential and Parallel Blocks
138
410 Exercises
140
Module Hierarchy
143
52 Parameters
146
53 Arrays of Instances
150
54 Generate Blocks
151
55 Exercises
154
Logic Level Modeling
156
62 Logic Gates and Nets
158
621 Modeling Using Primitive Logic Gates
159
622 FourLevel Logic Values
162
623 Nets
163
624 A Logic Level Example
166
63 Continuous Assignment
171
631 Behavioral Modeling of Combinational Circuits
172
632 Net and Continuous Assign Declarations
174
64 A Mixed BehavioralStructural Example
176
65 Logic Delay Modeling
180
651 A Gate Level Modeling Example
181
652 Gate and Net Delays
182
653 Specifying Time Units
185
651 Minimum Typical and Maximum Delays
186
66 Delay Paths Across a Module
187
73 MealyMoore Machine Specifications
203
731 A Complex Control Specification
204
74 Introduction to Behavioral Synthesis
209
75 Summary
210
Advanced Timing
211
82 Basic Model of a Simulator
214
821 Gate Level Simulation
215
823 Scheduling Behavioral Models
218
83 NonDeterministic Behavior of the Simulation Algorithm
220
831 Near a Black Hole
221
832 Its a Concurrent Language
223
84 NonBlocking Procedural Assignments
226
842 Prevalent Usage of the NonBlocking Assignment
227
843 Extending the EventDriven Scheduling Algorithm
228
844 Illustrating NonBlocking Assignments
231
85 Summary
233
86 Exercises
234
UserDefined Primitives
239
91 Combinational Primitives
240
912 Describing Combinational Logic Circuits
242
92 Sequential Primitives
243
921 LevelSensitive Primitives
244
93 Shorthand Notation
246
95 Summary
249
Switch Level Modeling
251
102 Switch Level Modeling
256
1022 Strength Definitions
259
1023 An Example Using Strengths
260
1024 Resistive MOS Gates
262
103 Ambiguous Strengths
263
1031 Illustrations of Ambiguous Strengths
264
1032 The Underlying Calculations
265
104 The miniSim Example
270
1042 The miniSim Source
271
1043 Simulation Results
280
105 Summary
281
Projects
283
1111 Modeling Power Dissipation
284
1113 Steps
285
112 A Floppy Disk Controller
286
1122 Disk Format
287
1123 Function Descriptions
288
1124 Reality Sets In
291
1126 Supporting Verilog Modules
292
Tutorial Questions and Discussion
293
A2 Testbench Modules
303
A4 Sequential Circuits
305
A5 Hierarchical Descriptions
308
Lexical Conventions
309
B2 Operators
310
B4 Strings
311
B5 Identifiers System Names and Keywords
312
Verilog Operators
314
C2 Operator Precedence
320
C3 Operator Truth Tables
321
C4 Expression Bit Lengths
322
Verilog Gate Types
323
D2 BUF and NOT Gates
325
D3 BUFIF and NOTIF Gates
326
D4 MOS Gates
327
D5 Bidirectional Gates
328
Registers Memories Integers and Time
329
E2 Memories
330
E3 Integers and Times
331
System Tasks and Functions
333
F2 Continuous Monitoring
334
F3 Strobed Monitoring
335
F5 Simulation Time
336
F8 Reading Data From Disk Files
337
Formal Syntax Definition
339
G2 Source text
343
G3 Declarations
346
G4 Primitive instances
351
G5 Module and generated instantiation
353
G6 UDP declaration and instantiation
354
G7 Behavioral statements
355
G8 Specify section
359
G9 Expressions
365
G10 General
370
Index
373
Copyright

Other editions - View all

The Verilog® Hardware Description Language
Donald E. Thomas,Philip R. Moorby
Limited preview - 2002
The Verilog® Hardware Description Language
Donald E. Thomas,Philip R. Moorby
Limited preview - 2013
The Verilog® Hardware Description Language
Donald E. Thomas,Philip R. Moorby
Limited preview - 2007
View all »

Common terms and phrases

adder assign statement attribute_instance begin behavioral model binaryToESeg bus master bytes casez clock edge clock signal combinational logic constant_expression continuous assignment currentState cycle-accurate dataLines datapath declared DEdgeFF default defined delay delay3 described drive strength element encoded end endmodule Example endcase eSeg event control event list executed expression fanout Figure fillBits finite state machine flip flop full adder function gate instances gate level gate primitives getMask identifier IEEE Std illustrates implementation initial statement inout integer latch loaded Logic Gates logic synthesis logic values loop ment module nand gate negedge nextState non-blocking assignment operands operator output reg parameter ports posedge clock positive edge procedural assignment procedural statements reset scheduled sensitivity list sequential shown in Example signal signed simulation specified StrongO syntax synthesis tool task trireg update event Verilog Verilog description wait wire write xor gates zero

References to this book

SPECC: Specification Language and Methodology
Daniel D. Gajski
No preview available - 2000
Hardware/Software Co-Design: Principles and Practice
Jørgen Staunstrup,Wayne Wolf
Limited preview - 1997
All Book Search results »

Bibliographic information

QR code for The Verilog® Hardware Description Language
TitleThe Verilog® Hardware Description Language
AuthorsDonald Thomas, Philip Moorby
Edition5, illustrated
PublisherSpringer Science & Business Media, 2008
ISBN0387853448, 9780387853444
Length386 pages
Subjects ›  ›  › 

Computers / CAD-CAM
Technology & Engineering / Electrical
Technology & Engineering / Electronics / Circuits / General
Technology & Engineering / Electronics / General
  
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