The Verilog® Hardware Description LanguageXV From the Old to the New xvii Acknowledgments xx| Verilog A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits 11 Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Procedural Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment (" |
Contents
2247 | 18 |
Tying Behavioral and Structural Models Together | 25 |
Module Hierarchy | 34 |
Behavioral Modeling 73 | 72 |
Concurrent Processes | 109 |
Module Hierarchy | 143 |
Logic Gates and Nets | 158 |
CycleAccurate Specification | 195 |
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The Verilog® Hardware Description Language Donald E. Thomas,Philip R. Moorby No preview available - 2014 |
Common terms and phrases
adder addr assign statement attribute_instance begin end behavioral model binaryToESeg bus master bytes casez circuit clock edge clock signal combinational logic consReady constant_expression continuous assignment cycle cycle-accurate dataLines datapath declared DEdgeFF default defined delay described disable drive strength element end endmodule endcase endmodule Example eSeg evaluated event control event list executed expression fanout Figure fillBits finite state machine flip flop function gate level gate primitives getMask hierarchical name iClear identifier illustrates implementation initial statement inout input instruction register integer latch loaded logic synthesis logic values loop ment module multiply NAND gate negedge nextState non-blocking assignment operands operator output reg parameter ports posedge clock positive edge procedural assignment qout reset scheduled sensitivity list sequential shown in Example signal signed simulation specified synchronize synthesis tool task two's complement update event Verilog wire write XOR gates zero