Algorithms for VLSI Physical Design AutomationAlgorithms for VLSI Physical Design Automation, Second Edition is a core reference text for graduate students and CAD professionals. Based on the very successful First Edition, it provides a comprehensive treatment of the principles and algorithms of VLSI physical design, presenting the concepts and algorithms in an intuitive manner. Each chapter contains 3-4 algorithms that are discussed in detail. Additional algorithms are presented in a somewhat shorter format. References to advanced algorithms are presented at the end of each chapter. Algorithms for VLSI Physical Design Automation covers all aspects of physical design. In 1992, when the First Edition was published, the largest available microprocessor had one million transistors and was fabricated using three metal layers. Now we process with six metal layers, fabricating 15 million transistors on a chip. Designs are moving to the 500-700 MHz frequency goal. These stunning developments have significantly altered the VLSI field: over-the-cell routing and early floorplanning have come to occupy a central place in the physical design flow. This Second Edition introduces a realistic picture to the reader, exposing the concerns facing the VLSI industry, while maintaining the theoretical flavor of the First Edition. New material has been added to all chapters, new sections have been added to most chapters, and a few chapters have been completely rewritten. The textual material is supplemented and clarified by many helpful figures. Audience: An invaluable reference for professionals in layout, design automation and physical design. |
Contents
| 1 | |
| 2 | |
Foreword | 9 |
field Topics include the VLSI design cycle physical design cycle design styles | 19 |
These topics play a key role in determining the layout of high | 46 |
we give pointers to the readers for advanced topics An extensive bibliography | 55 |
Data Structures and Basic Algorithms | 81 |
3 | 88 |
Detailed Routing | 269 |
1 | 308 |
OvertheCell Routing and Via Minimization | 345 |
Specialized Routing | 393 |
Compaction | 423 |
Physical Design Automation of FPGAs | 451 |
| 497 | |
| 529 | |
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Common terms and phrases
3D-switchbox blocks boundary called channel routing problem chip circle graphs circuit clock cluster CMOS compaction complexity components computed connected constraint graph corner stitch cost cutsize data structure delay design automation design cycle design rules design style detailed routing doglegs edge example floorplanning FPGA full custom gate array given graph G grid graph horizontal input integer program interconnect intersection interval graph iteration layout line segments maximum independent set method minimize minimum neighbor node NP-complete number of nets objective function optimal output over-the-cell partitioning algorithms partitioning problem permutation graph phase physical design pin assignment placement algorithms placement problem planar plist rectangles rectilinear Steiner tree reduce router routing algorithms routing region shortest path shown in Figure simulated annealing solution standard cell standard cell design Steiner tree subcircuits switchbox techniques terminals total number tracks transistor vertex vertical constraint VLSI wafer weight width wire length