VHDL: Analysis and Modeling of Digital SystemsHere's the new second edition of the authoritative reference engineers need to guide them through the use of VHDL hardware description language in the analysis, simulation, and modeling of complicated microelectronic circuits. You'll find extensive new material to bring the guide fully up to date with the new VHDL93 standard, including new chapters on design flow, interfacing, modeling, and timing. Extensive appendixes, including ones on logic synthesis and CPU description styles, provide up-to-date information on the use of VHDL in design. The number and depth of its relevant and practical examples and problems is what sets this edition apart from other VHDL texts. |
Contents
Digital System Design Process | 1 |
1 | 15 |
VHDL Background | 21 |
Copyright | |
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a_eq_b a_gt_b adbus apply_data ARCHITECTURE behavioral array average_delay basic_utilities package BEGIN behavioral description BIT VECTOR bit_comparator BLOCK clk block statement BOOLEAN busses byte cache cbit Chap circuit clock comp1 concurrent databus dataflow description dbus DOWNTO drivers ELSIF END BLOCK END COMPONENT END LOOP END PROCESS entity declaration enumeration type example Figure flip-flop gate_level guarded signal hardware description languages INOUT input instantiation instruction INTEGER interface ir_lines logic value memory NAND gate nand2 netlist next_state nibble nibble_comparator node opcode operand operation output parameters Parwan PORT MAP procedure process statement qit_vector read_mem reset resolution function RETURN qit RETURN std_logic_vector sequential shown in Fig shows signal assignment simulation single_delay specified std_logic structural subprogram SUBTYPE target2 test bench tion tphl tplh transaction type conversion VECTOR 3 DOWNTO VHDL description VHDL language WAIT waveform wiring write write_mem XOR gate