Hardware-Software Co-Synthesis of Distributed Embedded SystemsEmbedded computer systems use both off-the-shelf microprocessors and application-specific integrated circuits (ASICs) to implement specialized system functions. Examples include the electronic systems inside laser printers, cellular phones, microwave ovens, and an automobile anti-lock brake controller. Embedded computing is unique because it is a co-design problem - the hardware engine and application software architecture must be designed simultaneously. Hardware-Software Co-Synthesis of Distributed Embedded Systems proposes new techniques such as fixed-point iterations, phase adjustment, and separation analysis to efficiently estimate tight bounds on the delay required for a set of multi-rate processes preemptively scheduled on a real-time reactive distributed system. Based on the delay bounds, a gradient-search co-synthesis algorithm with new techniques such as sensitivity analysis, priority prediction, and idle- processing elements elimination are developed to select the number and types of processing elements in a distributed engine, and determine the allocation and scheduling of processes to processing elements. New communication modeling is also presented to analyze communication delay under interaction of computation and communication, allocate interprocessor communication links, and schedule communication. Hardware-Software Co-Synthesis of Distributed Embedded Systems is the first book to describe techniques for the design of distributed embedded systems, which have arbitrary hardware and software topologies. The book will be of interest to: academic researchers for personal libraries and advanced-topics courses in co-design as well as industrial designers who are building high-performance, real-time embedded systems with multiple processors. |
Other editions - View all
Hardware-Software Co-Synthesis of Distributed Embedded Systems Ti-Yen Yen,Wayne Wolf No preview available - 2010 |
Hardware-Software Co-Synthesis of Distributed Embedded Systems Ti-Yen Yen,Wayne Wolf No preview available - 2014 |
Common terms and phrases
allocation and scheduling application software approach ASIC Bprt buffer bus scheduling buses calculated Chapter co-synthesis algorithm communication process computer-aided design data dependencies delay estimation distributed system dummy processes embedded system architecture embedded system design Equation 2.2 example execution feasible Figure fixed-point iteration FPGA fractional deadline function hard cost constraint hard deadline hardware and software hardware engine hardware-software co-design hardware-software partition heuristics higher priority idle-PE elimination implementation initial solution integer linear programming interface LatestTimes linear longest path lower bound maximum separation MaxSeparations multiple node NP-hard optimization P.request P₁ P₂ performance analysis phase adjustment Prakash and Parker's priority assignment problem process computation programming R₁ random-3 rate constraints rate-monotonic scheduling reallocation receiving process running satisfied scheduling theory Section sensitivity simulated annealing soft deadline software architecture specification system cost Table task delay task graph task period techniques topologically sorted upper bound Verilog VHDL worst-case delay worst-case response