The VerilogŪ Hardware Description Language

Front Cover
Springer Science & Business Media, Mar 14, 2013 - Technology & Engineering - 354 pages
XV Acknowledgments xvii Chapter 1 Verilog - A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits II Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Behavioral Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines IS Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment("
 

Contents

Behavioral Modeling
46
Concurrent Processes
81
Logic Level Modeling
115
21
155
Advanced Timing
159
Logic Synthesis
189
Behavioral Synthesis
213
UserDefined Primitives
227
Appendix A Tutorial Questions and Discussion
283
22
299
Appendix B Lexical Conventions
301
Verilog Gate Types
313
Appendix E Registers Memories Integers and Time
319
Appendix G Formal Syntax Definition 329
328
33
347
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