The VerilogŪ Hardware Description LanguageXV Acknowledgments xvii Chapter 1 Verilog - A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits II Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Behavioral Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines IS Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment(" |
Contents
Behavioral Modeling | 46 |
Concurrent Processes | 81 |
Logic Level Modeling | 115 |
21 | 155 |
Advanced Timing | 159 |
Logic Synthesis | 189 |
Behavioral Synthesis | 213 |
UserDefined Primitives | 227 |
Projects | 273 |
Other editions - View all
The Verilog Hardware Description Language Donald E. Thomas,Donald E., Thomas,Philip R. Moorby No preview available - 1998 |
The Verilog(r) Hardware Description Language Donald E. Thomas,Philip R. Moorby No preview available - 2014 |
Common terms and phrases
addr assign statement begin end behavioral model behavioral synthesis bus master bytes circuit clock edge clock event clock period clock signal combinational logic compiler directive control path currentState cycle cycle-accurate dataLines dataOut datapath declared DEdgeFF default defined delay described drive element encoded end endmodule endcase endmodule Example eSeg evaluation events event control event list executed expression fanout fillBits finite state machine flip flop full adder function gate instantiations gate level iClear implementation initial statement inout instance latch loaded logic synthesis logic values loop ment module NAND gate negedge nextState non-blocking assignment operands output q parameter ports posedge clock positive edge procedural assignment procedural statements qout reset scheduled sensitivity list sequential shown in Example signal simulation specified start_pos strength synchronize synthesis tool task update event vector Verilog wait wire write xin1 XOR gates zero