Pentium Processor System Architecture

Front Cover
Addison-Wesley Professional, 1995 - Computers - 433 pages
Pentium Processor System Architecture describes the hardware architecture of computers using Intel's family of Pentium processors, providing a clear, concise explanation of the microprocessor's relationship to the rest of the system.
Written for computer hardware and software engineers, this book details Intel's technical strategy behind the Pentium family of processors - not just how Intel designed Pentium, but why. This revised edition expands coverage of virtually every topic and adds new sections on the Pentium 90 and 100MHz (P54C) processors. In addition to pointing out the key differences between 80486 and Pentium system designs, the book explores all the important Pentium features.
 

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Contents

Documentation Conventions
4
Table 11 Prefetch Queue Depth
4
Faster Memory Accesses
4
The Pentium 60 and 66MHz Processors
21
Functional Unit Description
28
Pentium Cache Overview
35
Caching Solution
50
Multiple Processors and the MESI Model
61
Table 77 Signals Placed on the Bus During a Pipelined Cycle
191
The L2 Cache Lookup Cycle
192
Cycle B Begins
198
Anatomy of a Write Hit
204
Table 81 Pentium Processor Bus Cycle Types
210
Single Transfer NonBurst Bus Cycles
211
Table 82 Special Cycles
216
Interrupt Acknowledge Bus Cycle
217

Multiprocessor MESI ImplementationThe Life and Times
70
Table 42 Initial State of Cache Lines
72
Table 43 Initial State of Cache Lines
80
Table 44 L1 Cache State Changes During Memory Reads
89
Pentium Signal Interface
93
Table 51 486 Signals Not Used by the Pentium Processor
95
Table 57 Pentium Processor Addressing Examples
101
The Data Bus
103
Communication with 81632 and 64bit Devices
105
Bus Cycle Control Signals
113
Table 59 Pentium Processor Bus Cycle Definition
114
Strong Write OrderingEWBE+
121
Table 511 State of the PCD Pin During Memory Accesses
125
Interrupt Signals
126
Debugſtest Signals
133
Rules for Integer Instruction Pairing
145
Table 61 Examples of Explicit Register Contention
147
Instruction Branch Prediction
149
SplitLine Access
157
Table 62 FloatingPoint Pipeline Stages
159
The Data Cache and Burst Bus Cycles
163
Table 71 Data Cache Directory Entries Prior to Sample Reads
169
Anatomy of a Read Miss
172
Table 73 Bus Cycle Definition for Cache Linefill Request
177
L2 Cache Hit Pipelined access
180
Table 75 Quadword Address Sequences During Burst Transfers
185
System Management Mode SMM
221
Table 91 Initial Core Register Values for
231
Executing SMI Handler
233
Parity and Bus Cycle Verification
239
Debug Extensions
247
Table 102 Internal Hardware Statistics and Index Number
250
Incompatibilities
253
Table 111 Bus Transaction Parity Error Action Table
258
Program Debug Features
270
P54C Processor Overview
281
Dual Processor Signals
287
Dual Processors
295
Bus Arbitration in a DualProcessor System
298
Address Snooping in a DualProcessor System
304
The APIC
317
Local Interrupts LINTs Timer Error
337
InterProcessor Interrupts IPI
343
Summary of Interrupt Distribution and Handling
356
Local APIC Register Mapping
370
SMI Delivery via APIC
376
The Pentium 61075MHz Processor
381
Glossary of Terms
389
Signal Glossary
405
Instruction Pairing Summary
423
Copyright

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About the author (1995)

MindShare, Inc. is one of the leading technical training companies in the hardware industry, providing innovative courses for dozens of companies, including Intel, IBM, and Compaq.

Don Anderson is the author of many MindShare books. He passes on his wealth of experience in digital electronics and computer design by training engineers, programmers, and technicians for MindShare.

Tom Shanley, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.



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