Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI CircuitsThe modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers. |
Contents
| 3 | |
| 13 | |
| 17 | |
Summary | 34 |
TEST ECONOMICS AND PRODUCT QUALITY | 35 |
LOGIC AND FAULT SIMULATION | 82 |
Modeling Levels and Types of Simulators | 91 |
5 | 105 |
MODELBASED ANALOG AND MIXEDSIGNAL TEST | 385 |
DELAY TEST | 417 |
DIGITAL DFT AND SCAN DESIGN | 465 |
Summary | 485 |
SRAM BIST with MISR | 534 |
BOUNDARY SCAN STANDARD | 549 |
ANALOG TEST BUS STANDARD | 575 |
SYSTEM TEST AND COREBASED DESIGN | 594 |
COMBINATIONAL CIRCUIT TEST GENERATION | 155 |
SEQUENTIAL CIRCUIT TEST GENERATION | 211 |
MEMORY TEST | 257 |
Relation Between Fault Models and Physical Defects | 276 |
RAM Test Hierarchy | 295 |
DSPBASED ANALOG AND MIXEDSIGNAL TEST | 309 |
THE FUTURE OF TESTING | 613 |
B PRIMITIVE POLYNOMIALS OF DEGREE 1 TO 100 | 619 |
| 638 | |
| 671 | |
Other editions - View all
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI ... M. Bushnell,Vishwani Agrawal No preview available - 2013 |
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI ... M. Bushnell,Vishwani Agrawal No preview available - 2004 |
Common terms and phrases
active additional algorithm allows analog applied assume ATPG base bits boundary called causes cell Chapter chip circuit clock combinational complexity components compute condition Consider contains cost coupling delay detected determine device DRAM effect element Equation error example fail failure fault coverage fault model fault simulation Figure flip-flops frequency function gate given graph hardware increase initial input known logic logic gate manufacturing means measurement memory method multiple needed node noise observability obtained operation output parameters path pattern performance phase pins possible present primary problem produce propagation provides reduce represents requires response result sampling scan selected sensitive sequence sequential shown shows signal single specific stuck-at faults synchronous Table testability time-frame transistor transition types unit vector verify VLSI voltage waveform write