Verilog — 2001: A Guide to the New Features of the Verilog Hardware Description Languageby Phil Moorby The Verilog Hardware Description Language has had an amazing impact on the mod em electronics industry, considering that the essential composition of the language was developed in a surprisingly short period of time, early in 1984. Since its introduc tion, Verilog has changed very little. Over time, users have requested many improve ments to meet new methodology needs. But, it is a complex and time consuming process to add features to a language without ambiguity, and maintaining consistency. A group of Verilog enthusiasts, the IEEE 1364 Verilog committee, have broken the Verilog feature doldrums. These individuals should be applauded. They invested the time and energy, often their personal time, to understand and resolve an extensive wish-list of language enhancements. They took on the task of choosing a feature set that would stand up to the scrutiny of the standardization process. I would like to per sonally thank this group. They have shown that it is possible to evolve Verilog, rather than having to completely start over with some revolutionary new language. The Verilog 1364-2001 standard provides many of the advanced building blocks that users have requested. The enhancements include key components for verification, abstract design, and other new methodology capabilities. As designers tackle advanced issues such as automated verification, system partitioning, etc., the Verilog standard will rise to meet the continuing challenge of electronics design. |
Contents
Foreword by Phil Moorby | 1 |
Introduction | 3 |
Whats new in Verilog2001 | 7 |
Combined port and data type declarations | 8 |
ANSI C style module declarations | 10 |
Module port parameter lists | 12 |
ANSI C style UDP declarations | 14 |
Variable initial value at declaration | 16 |
Power operator | 54 |
Attributes | 56 |
Sized and typed parameter constants | 59 |
Explicit inline parameter redefinition | 62 |
Fixed local parameters | 64 |
Standard random number generator | 66 |
Extended number of open files | 67 |
Enhanced file IO | 70 |
ANSI C style taskfunction declarations | 18 |
Automatic reentrant tasks | 20 |
Automatic recursive functions | 22 |
Constant functions | 24 |
Comma separated sensitivity lists | 26 |
Combinational logic sensitivity lists | 28 |
Implicit nets for continuous assignments | 32 |
Disabling implicit net declarations | 34 |
Variable vector part selects | 36 |
Multidimensional arrays | 38 |
Arrays of net and real data types | 40 |
Array bit and part selects | 41 |
Signed reg net and port declarations | 42 |
Signed based integer numbers | 44 |
Signed functions | 46 |
Sign conversion system functions | 48 |
Arithmetic shift operators | 50 |
Assignment width extension past 32 bits | 52 |
String read and write system tasks | 76 |
Enhanced invocation option testing | 78 |
Enhanced conditional compilation | 80 |
Source file and line compiler directive | 82 |
Generate blocks | 84 |
Configurations | 90 |
Ondetect pulse error propagation | 94 |
Negative pulse detection | 96 |
Enhanced input timing checks | 98 |
Negative input timing constraints | 100 |
Enhanced SDF file support | 102 |
Extended VCD files | 104 |
Enhanced PLA system tasks | 106 |
Enhanced Verilog PLI support | 107 |
Verilog2001 formal definition | 109 |
Verilog2001 reserved words | 131 |
133 | |
Other editions - View all
Verilog — 2001: A Guide to the New Features of the Verilog® Hardware ... Stuart Sutherland No preview available - 2012 |
Verilog — 2001: A Guide to the New Features of the Verilog® Hardware ... Stuart Sutherland No preview available - 2001 |
Common terms and phrases
ANSI C style arguments Arithmetic shift array attribute_instance Background Verilog-1995 binary byte Cadence Design Systems combinational logic compiler directive considerations This enhancement constant_expression continuous assignments Copyright 2001 IEEE data type declaration data_event default defparam delay3 end-of-file endmodule error expression file I/O file_name following example fopen fseek genvar Hardware Description Language IEEE Std input wire integer invocation option list_of_param_assignments list_of_parameter_assignments list_of_path_outputs list_of_port_identifiers localparam logic value module adder module instance module port module_path_expression notify_reg operand operation output reg parameter redefinition path_delay_expression Phil Moorby port declarations port_identifier posedge pulse range_expression recrem redefined ref_event reference_event reg variable rights reserved SDF files sensitivity list signal name simulation software tools source code source file specify block statement string symbolic library syntax Synthesis considerations synthesis tools system tasks timing_check_limit tokens ungetc unsigned_number VCD file vector Verilog HDL Verilog language Verilog PLI Verilog standard Verilog-2001 adds What's new Verilog-2001 width