Verilog HDL: A Guide to Digital Design and Synthesis, Volume 1VERILOG HDL, Second Editionby Samir PalnitkarWith a Foreword by Prabhu GoelWritten forboth experienced and new users, this book gives you broad coverage of VerilogHDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard. Among its many features, this edition- bull; bull;Describes state-of-the-art verification methodologies bull;Provides full coverage of gate, dataflow (RTL), behavioral and switch modeling bull;Introduces you to the Programming Language Interface (PLI) bull;Describes logic synthesis methodologies bull;Explains timing and delay simulation bull;Discusses user-defined primitives bull;Offers many practical modeling tips Includes over 300 illustrations, examples, and exercises, and a Verilog resource list.Learning objectives and summaries are provided for each chapter. About the CD-ROMThe CD-ROM contains a Verilog simulator with agraphical user interface and the source code for the examples in the book. Whatpeople are saying about Verilog HDL- "Mr.Palnitkar illustrates how and why Verilog HDL is used to develop today'smost complex digital designs. This book is valuable to both the novice and theexperienced Verilog user. I highly recommend it to anyone exploring Verilogbased design." -RajeevMadhavan, Chairman and CEO, Magma Design Automation "Thisbook is unique in its breadth of information on Verilog and Verilog-relatedtopics. It is fully compliant with the IEEE 1364-2001 standard, contains allthe information that you need on the basics, and devotes several chapters toadvanced topics such as verification, PLI, synthesis and modelingtechniques." -MichaelMcNamara, Chair, IEEE 1364-2001 Verilog Standards Organization Thishas been my favorite Verilog book since I picked it up in college. It is theonly book that covers practical Verilog. A must have for beginners andexperts." -BerendOzceri, Design Engineer, Cisco Systems, Inc. "Simple,logical and well-organized material with plenty of illustrations, makes this anideal textbook." -Arun K. Somani, Jerry R. Junkins Chair Professor,Department of Electrical and Computer Engineering, Iowa State University, Ames PRENTICE HALL Professional Technical Reference Upper Saddle River, NJ 07458 www.phptr.com ISBN: 0-13-044911-3 |
Contents
Basic Concepts | 29 |
Time | 37 |
Modules and Ports | 49 |
GateLevel Modeling | 63 |
Dataflow Modeling | 89 |
Behavioral Modeling | 119 |
Event OR Control | 134 |
27 | 148 |
SwitchLevel Modeling | 235 |
UserDefined Primitives | 251 |
Programming Language Interface | 273 |
Logic Synthesis | 299 |
Unoptimized intermediate representation | 313 |
Advanced Verification Techniques | 341 |
Appendices | 361 |
B List of PLI Routines | 369 |
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Common terms and phrases
4-bit full adder 4-to-1 multiplexer access routines attribute_instance begin end behavioral bitwise Bitwise Operators c_in c_out char CMOS compiler directives conditional statement constant_expression continuous assignment counter D-flipflop dataflow default defined delay values digital circuit discussed display endmodule executed expression FIFO finite state machine flipflop formal verification fulladd4 functional verification gate-level netlist Hardware Description Language hierarchical name IEEE Standard Verilog implementation initial begin inout input integer keyword latch logic gates logic synthesis tool logic value loop modeling module instance monitoring nmos operands operators optimized output parameter value path delays pin-to-pin pmos port declarations primitive qbar r_loop reset ripple carry RTL description sequential UDP shown in Example specify blocks specparam Standard Verilog Hardware stimulus switches T_FF Table tasks and functions toggle truth table types user-defined system task utility routines variables vector Verilog description Verilog Hardware Description Verilog HDL Verilog simulator wire