Applications of VHDL to Circuit DesignRandolph E. Harr, Alec G. Stanculescu |
Contents
SwitchLevel Modeling in VHDL | 1 |
Modeling of Transmission Line Effects in Digital Circuits 43 | 42 |
Behavior Modeling of Mixed AnalogDigital Circuits | 73 |
Modeling of AnalogDigital Loops in VHDL | 99 |
Modeling Style Issues for Synthesis | 123 |
Other editions - View all
Applications of VHDL to Circuit Design Randolph E. Harr,Alec G. Stanculescu No preview available - 2012 |
Common terms and phrases
abstraction algorithm amplifier analog circuits analog signal analog_time_delta_real analog-digital array assert attribute begin behavioral models capacitor chapter charge pump clock constant d_val defined delay described detector disconnection distributed algorithm driver model driver output driving value end component end process END RECORD end VHDL entity declaration envelope detector example f logic f_convz filter gate level global hardware HDL synthesis IEEE implementation inout input integration interface ENTITY language linear driver logic simulators logic synthesis loop methodology netlist node node2 open-drain output voltage package parameter PORT MAP pvout reconnection reset resolved value result RETURN shown in Figure simulation cycle simulation model specific standard strength structure switch-level synthesis tool t_delay t_wlogic tline_node transfer function transistor transmission line UART value-system VARIABLE vco_out verified VGAIN VHDL model VHDL simulation VINN VINP volt vout zero